The present invention is directed to capacitors used in a memory cell structure and in particular those using a ferroelectric material for dielectric.
A ferroelectric memory cell uses a capacitor with a ferroelectric material as all or part of the dielectric between the plates of the capacitor. The plates are usually flat and generally planar. Generally, the remanent polarization of dipoles in the ferroelectric material is the physical phenomenon or attribute by which data is stored in a non-volatile memory, as outlined in, e.g., Ramtron's U.S. Pat. Nos. 4,873,664 ("Self Restoring Ferroelectric Memory") and 4,893,272 ("Ferroelectric Retention Method"). In addition, ferroelectric capacitors can be used in volatile memory cells also, as in Ramtron's Australia Patent No. AU-B-25817/88 ("Charge Magnified DRAM Cell"). Furthermore, Ramtron's U.S. Pat. No. 5,005,102 ("Multilayer Electrodes For Integrated Circuit Capacitors") to the present inventor discloses a multilayer capacitor structure in an integrated circuit.
Currently, ferroelectric memory cells are laid out one of two ways. One lay-out locates the ferroelectric capacitor directly above a source/drain contact, as in Ramtron's European Patent Publication 396,221 ("Integrated Ferroelectric Capacitor") and European Patent Publication 338,157 ("Charge Magnified DRAM CELL"). The ferroelectric material thereby contacts a transistor via the source/drain contact and a bottom electrode of the capacitor. Material and process limitations can impede practical implementation of this layout because the interface between the bottom electrode and the substrate (usually silicon) in the source/drain contact is unstable at the temperature required for subsequent processing.
In another layout, a ferroelectric capacitor is located adjacent to a transistor. A source/drain contact is connected to the capacitor using aluminum metallization. The memory cell, using this layout requires a larger area, making it less attractive for use in high density memory products.
Another problem with the current designs for a ferroelectric capacitor involves the fabrication of a top electrode. With current methods, the top electrode is defined by a deposition and lithographic step. An insulating layer is then deposited over the top electrode, and a contact to the top electrode is then processed. Accordingly, the top electrode has to be sufficiently large in size to insure that the contact or hole through the insulating layer is (completely) within the boundary of the top electrode. As a result, a larger than desired top electrode area is required. Such an oversized top electrode is not desirable because it requires a larger area than other methods, making it less attractive for high density memory products.
The main object of the present invention is to provide a method and structure for a ferroelectric capacitor to be coupled to a switching device, e.g. a transistor, which does not suffer from the drawbacks described above.